Education
Massachusetts Institute of Technology Cambridge, MA — May 2029
B.S.E. in Electrical Engineering with Computing · GPA 5.0/5.0- Courses: Algorithms, Grad Computer System Architecture, Embedded Systems, Computational Structures
Research & Work
Zero ASIC - TPU Chiplet Engineering — Full Stack Accelerator Designer Intern - Part Time Cambridge, MA · Aug 2026–Present
- Designing open source TPU chiplet for edge inference - flexible systolic array core, minimize J/TOP
- Working on HW/SW Co-design -> Architecture -> RTL -> Synthesis, PNR -> Verification -> Tapeout on TSMC 12nm
MIT FLAME Lab - GPU Design — Student Researcher - Part Time Cambridge, MA · Aug 2026–Present
- Designing high performance open source GPU with full HW/SW Co-Design
- Tapeout planned for 2027 provided architecture and results are promising
MIT Low Energy Autonomous Navigation Group — Student Researcher - Full Time Cambridge, MA · May 2026–Sep 2026
- Designing 3D Gaussian Splatting FPGA Renderer for robotics platforms with real-time usage in SLAM and low power robots.
MIT Ferroelectric Materials & Devices Group — Student Researcher - Part Time Cambridge, MA · Aug 2025–May 2026
- Improving on-chip energy storage using ferroelectric material effects.
- Tested wafers, analyzed, and optimized novel capacitors for energy, power density
UC Berkeley Nanotechnology Lab — Student Researcher - Part Time Hybrid/Berkeley, CA · Jun 2024–Aug 2025
- Built low-cost 18-channel microfluidics potentiostat & ECG hardware via Teensy optimization
- Created FPGA firmware and C# driver for a 256-channel electrochemical camera.
BWSI: BASICs of ASICs, MIT Lincoln Labs — Student - Full Time Virtual · Jun 2024–Jul 2024
- Learned ASIC fabrication, ASIC design, Verilog verification, simulation
- Led team of 6 to design and tape out beamforming ASIC, tapedout 7 other accelerators
Projects
Dawn CPU - Out of Order RV32 CPU Core with DDR4 Support Sep 2025–Present
- Full OOO Risc-V Core with Compiler and Toolchain Support. DDR4 Memory, Split I/D non-blocking cache with arbitration
- Runs DOOM on Kintex Ultrascale FPGA at 60fps, 250 Mhz Timing Closure. 7+ Million Instagram Views
- Planned Self-Funded tape out on GF180 along with full TPU GPU System on Chip in June 2027. Devboard Planned
Kernn - Fully Programmable Neural Network Accelerator Mar 2026–Present
- FPGA-based parameterizable Neural Network Accelerator based on systolic array.
- Tiled computation, Programmable for any pytorch DNN model within memory constraint.
- Planned integration with RISC-V core and two wide systolic pipelines for throughput
PDM Bitstream Operators for Efficient Beamforming - International ISEF 2nd Award Jul 2024–Sep 2025
- Leveraged microphone Pulse Density Modulated bitstreams to increase beamforming speed dramatically (250x runtime improvement) while lowering power demands
- Custom designed PCB hardware and built an FPGA-based acoustic camera.
Activities
MIT Open Compute Laboratory - Lead Aug 2025–Present
- Developed custom accelerators for DNNs; Demonstrated Ternary, INT8 Inference
- Designing custom FPGA server cluster with 100Gb/s+ inter-FPGA bandwidth
MIT Satellite Team Mar 2026–Present
- Designing custom electronics for LEONIRD High Altitude Balloon & CubeSat,
- Launched High Altitude Balloon and collected data at over 30,000 feet
MIT Motorsports Aug 2025–May 2026
- Designing custom motor inverters for racecar with 5x efficiency, 4x precision boost.
Awards
- Eigenprize 2nd Place $30k Grant
- Solved Jane Street ASIC Reverse Engineer Challenge
- MIT 6.191 Fastest CPU/NN Accelerator
- MakeMIT 2nd Award
- MIT Battlecode 2026 Finalist
- $15k Naval Research Award
- ISEF 2nd Award & 3rd Award
Skills
Technical: ASIC Design, Verilog, Chisel, Yosys/Librelane, C++, Python, Java, Altium, C#, Vivado, CAD, Wafer Probing
Hobbies: Taekwondo — Fourth Degree Black Belt, 12+ years
Checkout my full list of projects here.